www.irf.com 1 IRLR8503 parameter symbol IRLR8503 units drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain or source t c = 25c i d 44 a t c = 90c 32 pulsed drain current i dm 196 power dissipation t c = 25c p d 62 w t c = 90c 30 junction & storage temperature range t j , t stg ?55 to 150 c continuous source current (body diode) i s 15 a pulsed source current i sm 196 n-channel application-specific mosfet ideal for cpu core dc-dc converters low conduction losses minimizes parallel mosfets for high current applications description this new device employs advanced hexfet power mosfet technology to achieve very low on-resistance. the reduced conduction losses makes it ideal for high efficiency dc-dc converters that power the latest generation of microprocessors. the IRLR8503 has been optimized and is 100% tested for all parameters that are critical in synchronous buck converters including r ds(on) , gate charge and cdv/dt- induced turn-on immunity. the IRLR8503 offers an extremely low combination of q sw & r ds(on) for reduced losses in control fet applications. the package is designed for vapor phase, infra-red, convection, or wave soldering techniques. power dissipation of greater than 2w is possible in a typical pcb mount application. hexfet ? mosfet for dc-dc converters IRLR8503 v ds 30v r ds (on) 18 m ? q g 20 nc q sw 8 nc q oss 29.5 nc device ratings (max. values) IRLR8503 d-pak absolute maximum ratings parameter symbol max. units maximum junction-to-ambient r ja 50 c/w maximum junction-to-lead r jl 2.0 c/w thermal resistance current (v gs 10v) s d g pd-93839a 12/21/00
www.irf.com 2 IRLR8503 parameter symbol min typ max units conditions diode forward voltage* v sd ? 1.0 v i s = 15a , v gs = 0v reverse recovery charge q rr ? 76 nc di/dt = 700a/s v ds = 16v, v gs = 0v, i s = 15a reverse recovery charge q rr(s) ? 67 di/dt = 700a/s (with parallel schottky) (with 10bq040) v ds = 16v, v gs = 0v, i s = 15a parameter symbol min typ max units conditions drain-to-source v (br)dss 30 ?? vv gs = 0v, i d = 250a breakdown voltage* static drain-source r ds (on) ? 11 16 m ? v gs = 10v, i d =15a on resistance* ? 13 18 v gs = 4.5v, i d =15a gate threshold voltage* v gs (th) 1.0 v v ds = v gs , i d = 250a drain-source leakage current i dss ?? 30* a v ds = 24v, v gs = 0 ?? 150 v ds = 24v, v gs = 0, tj = 100 c gate-source leakage current* i gss ?? 100 na v gs = 12v total gate charge control fet* q g ? 15 20 v gs = 5v, i d = 15a, v ds =16v, total gate charge sync fet* q g ? 13 17 v gs = 5v, v ds < 100mv pre-vth q gs1 ? 3.7 ? v ds = 16v, i d = 15a gate-source charge post-vth q gs2 ? 1.3 ? nc gate-source charge gate to drain charge q gd ? 4.1 ? switch charge* (q gs2 + q gd )q sw ? 5.4 8 output charge* q oss ? 23 29.5 v ds = 16v, v gs = 0 gate resistance r g ? 1.7 ? ? turn-on delay time t d (on) ? 10 ? v dd = 16v, i d = 15a drain voltage rise time tr v ? 18 ? ns v gs = 5v turn-off delay time t d (off) ? 11 ? clamped inductive load drain voltage fall time tf v ? 3 ? see test diagram fig 14. input capacitance c iss ? 1650 ? output capacitance c oss ? 650 ? pf v ds = 25v, v gs = 0 reverse transfer capacitance c rss ? 58 ? electrical characteristics source-drain rating & characteristics notes: repetitive rating; pulse width limited by max. junction temperature. pulse width 300 s; duty cycle 2%. when mounted on 1 inch square copper board, t < 10 sec. * devices are 100% tested to these parameters. typ = measured - q oss calculated continuous current based on maximum allowable junction temperature; switching and other losses will decrease rms current capability; package limitation current = 20a.
www.irf.com 3 IRLR8503 device capacitance corresponding charge parameter c gs q gs c gs + c gd q g c gd q gd power mosfet optimization for dc-dc converters while the irlr8103v and IRLR8503 can and are be- ing used in a variety of applications, they were designed and optimized for low voltage dc-dc conversion in a synchronous buck converter topology, specifically, mi- croprocessor power applications. the IRLR8503 (fig- ure 1) was optimized for the control fet socket, while the irlr8103v was optimized for the synchronous fet function. because of the inter-electrode capacitance (figure 2) of the power mosfet, specifying the r dson of the de- vice is not enough to ensure good performance. an optimization between r dson and charge must be per- formed to insure the best performing mosfet for a given application. both die size and device architec- ture must be varied to achieve the minimum possible in-circuit losses. this is independently true for both control fet and synchronous fet. unfortunately, the capacitances of a fet are non-linear and voltage de- pendent. therefore, it is inconvenient to specify and use them effectively in switching power supply power loss estimations. this was well understood years ago and resulted in changing the emphasis from capaci- tance to gate charge on power mosfet data sheets. international rectifier has recently taken the industry a step further by specifying new charge parameters that are even more specific to dc-dc converter de- sign (table 2). in order to understand these parameters, it is best to start with the in-circuit waveforms in fig- ure 3 & figure 4. figure 1 ? application topology figure 2 ? inter-electrode capacitance table 1 ? traditional charge parameters table 2 ? new charge parameters figure 3 ? control fet waveform figure 4 ? sync fet waveform new charge parameter description waveform q gs1 pre-threshold gate charge q gs2 post-threshold gate charge figure 3 q gcont control fet total q g q switch charge during control fet switching combines q gs2 and q gd q oss output charge figure 5 charge supplied to c oss during the q gd figure 6 period of control fet switching q gsync synchronous fet total q g (v ds 0) figure 4 the waveforms are broken into segments correspond- ing to charge parameters. these, in turn, correspond to discrete time segments of the switching waveform. losses may be broken into four categories: conduc- tion loss, gate drive loss, switching loss, and output loss. the following simplified power loss equation is true for both mosfets in a synchronous buck con- verter: for the synchronous fet, the p switch term becomes virtually zero and is ignored. p loss = p conduction + p gate drive + p switch + p output figure 5 ? q oss equivalent circuit figure 6 ? q oss waveforms coss1 2n IRLR8503 (cont fet) irlr8103v (sync fet) cgd cgs cds drain voltage gate voltage drain current qgd qgs1 qgs2 vgth qswitch qg (control fet) drain voltage 0 v gate voltage 0 a drain current dead time vgth body diode current qg (sync fet) g1 g2 n1 cont fet n2 sync fet sn coss2 2n vin switch node voltage (vsn) n1 gate voltage n1 current n1 coss discharge + n2 coss charge
www.irf.com 4 IRLR8503 table 3 and table 4 describes the event during the various charge segments and shows an approximation of losses during that period. table 3 ? control fet losses table 4 ? synchronous fet losses conduction loss gate drive loss switching loss output loss losses associated with the q oss of the device every cycle when the control fet turns on. losses are caused by both fets, but are dissipated by the control fet. segment losses description losses associated with mosfet on time. i rms is a function of load current and duty cycle. losses associated with charging and discharging the gate of the mosfet every cycle. use the control fet q g . losses during the drain voltage and drain current transitions for every full cycle. losses occur during the q gs2 and q gd time period and can be simplified by using q switch . ) on ( ds rms cond r i p = 2 ? = g g in q v p ? ? ? g sw l in switch g gd l in qgd g gs l in qgs i q i v p i q i v p i q i v p 2 2 f v 2 q p in oss output = conduction loss gate drive loss switching loss output loss segment losses description losses associated with mosfet on time. i rms is a function of load current and duty cycle. losses associated with charging and discharging the gate of the mosfet every cycle. use the sync fet q g . generally small enough to ignore except at light loads when the current reverses in the output inductor. under these conditions various light load power saving techniques are employed by the control ic to maintain switching losses to a negligible level. losses associated with the q oss of the device every cycle when the control fet turns on. they are caused by the synchronous fet, but are dissipated in the control fet. dson rms cond r i p = 2 ? = g g in q v p 0 p switch ? = in oss output v q p 2 figure 7 . 2 & 3-fet solution for synchronous buck topology. i rlr8503 control fet (q1) 1 x irlr8103 or 2 x IRLR8503 synchronous f et (q2) typical pc application the irlr8103v and the IRLR8503 are suitable for synchronous buck dc-dc converters, and are optimized for use in next generation cpu applications. the irlr8103v is primarily optimized for use as the low side synchronous fet (q2) with low r ds(on) and high cdv/dt immunity.the IRLR8503 is primarily optimized for use as the high side control fet (q2) with low cobmined qsw and r ds(on) , but can also be used as a synchronous fet. the IRLR8503 is also tested for cdv/dt immunity, critical for the low side socket. the typical configuration in which these devices may be used in shown in figure 7. v or
www.irf.com 5 IRLR8503 figure 10. typical rds(on) vs. gate-to-source voltage figure 8. normalized on-resistance vs. temperature IRLR8503 typical characteristics figure 9. gate-to-source voltage vs. typical gate charge figure 11. typical capacitance vs. drain-to-source voltage figure 12. typical transfer characteristics 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c ) 0.5 1.0 1.5 2.0 2.5 r ds(on) , drain-to-source on resistance (normalized) i d = 15a v gs = 4.5v 0 4 8 12 16 q g, total gate charge (nc) 0.0 2.0 4.0 6.0 v g s , gate-to-source voltage (v) i d = 15a v ds = 20v 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 v gs, gate -to -source voltage (v) 0.010 0.011 0.012 0.013 0.014 0.015 r ds(on) , drain-to -source o n resistance ( ? ) i d = 15a 1 10 100 0 500 1000 1500 2000 2500 v , drain-to-source voltage (v) c, capacitance (pf) ds v c c c = = = = 0v, c c c f = 1mhz + c + c c shorted gs iss gs gd , ds rss gd oss ds gd c iss c oss c rss 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v gs , gate-to-source voltage (v) 1.0 10.0 100.0 1000.0 i d , drain-to-source current ( ) t j = 25 c t j = 150 c v ds = 15v 20s pulse width
www.irf.com 6 IRLR8503 inductive load circuit 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) figure 13. maximum effective transient thermal impedance, junction-to-ambient figure 14. clamped inductive load test diagram figure 15. switching waveform
www.irf.com 7 IRLR8503 package outline to-252aa outline dimensions are shown in millimeters (inches) to-252aa (d-pak) part marking information 6.73 ( .265 ) 6.35 ( .250 ) - a - 4 1 2 3 6.22 ( .245 ) 5.97 ( .235 ) - b - 3x 0.89 ( .035 ) 0.64 ( .025 ) 0.25 ( .010 ) m a m b 4.57 ( .180 ) 2.28 ( .090 ) 2x 1.14 ( .045 ) 0.76 ( .030 ) 1.52 ( .060 ) 1.15 ( .045 ) 1.02 ( .040 ) 1.64 ( .025 ) 5.46 ( .215 ) 5.21 ( .205 ) 1.27 ( .050 ) 0.88 ( .035 ) 2.38 ( .094 ) 2.19 ( .086 ) 1.14 ( .045 ) 0.89 ( .035 ) 0.58 ( .023 ) 0.46 ( .018 ) 6.45 ( .245 ) 5.68 ( .224 ) 0.51 ( .020 ) min. 0.58 ( .023 ) 0.46 ( .018 ) lead assignments 1 - g at e 2 - d ra in 3 - s o u r c e 4 - d ra in 10.42 ( .410 ) 9.40 ( .370 ) notes: 1 dimensioning & tolerancing per ansi y14.5m, 1982. 2 controlling dimension : inch. 3 c o n fo r m s t o jed e c o u tlin e to -252aa . 4 dimensions show n are before solder dip, s o ld er d ip m a x. +0.16 ( .006 ) . international rectifier lo g o assembly lo t co de exa m ple : this is an irfr120 w ith a ss e m b ly l o t c o d e 9 u1 p first portion of part number second portion of part number 120 ir f r 9u 1p a
www.irf.com 8 IRLR8503 tape & reel information to-252aa tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl notes : 1. controlling dimension : millimeter. 2. all dimensions are show n in millimeters ( inches ). 3. outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch data and specifications subject to change without notice. this product has been designed and qualified for the commercial market. qualification standards can be found on ir ? s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 12/00
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